Ostoskori (0)
Huom! Käyttökatkos 1.6.2025
Huom! Tietosuojaselostetta on taas päivitetty Lue lisää
Standardi

IEEE 1364-2005

Enums.Sd.Shared.Models.DocumentStatus.Revised
Esikatsele

Lisää mahdolliset korjaukset ja lisäykset ostoskoriin alta.

Kieli
Toimitustavat

Soveltamisala

Revision Standard - Superseded. The Verilog hardware description language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine-readable and human-readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. The primary audiences for this standard are the implementers of tools supporting the language and advanced users of the language. (Supersedes IEEE Std 1364-2001. Superseded by IEEE Std 1800-2009).

Julkaisun tiedot

  • Standardi julkaisijalta IEEE
  • Julkaistu:
  • Julkaisutyyppi: IS
  • products.specs.pages
  • Publisher IEEE
  • Distributor IEEE
  • ICS 35.060
  • Tekninen komitea IEEE Computer Society / Design Automation

Sidokset