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Standard

IEEE 62530-2007

Revised

Note: This standard has a new edition: IEEE 62530-2011

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Corrigendums and amendments are bought separately.

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Abstract

New IEEE Standard - Superseded. This standard provides a set of extensions to the IEEE 1364™ Verilog® hardware description language (HDL) to aid in the creation and verification of abstract architectural level models. It also includes design specification methods, embedded assertions language, testbench language including coverage and an assertions application programming interface (API), and a direct programming interface (DPI). This standard enables a productivity boost in design and validation and covers design, simulation, validation, and formal assertion-based verification flows.

Document information

  • Standard from IEEE/IEC
  • Published:
  • Document type: IS
  • Pages
  • Publisher IEEE/IEC
  • Distributor IEEE/IEC
  • ICS 25.040
  • ICS 35.060
  • Technical Committee IEEE Computer Society / Design Automation