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Standard

IEEE 1800.2-2020

Published

Corrigendums and amendments are bought separately.

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Abstract

Revision Standard - Active. The Universal Verification Methodology (UVM) that can improve interoperability, reduce the cost of using intellectual property (IP) for new projects or electronic design automation (EDA) tools, and make it easier to reuse verification components is provided. Overall, using this standard will lower verification costs and improve design quality throughout the industry. The primary audiences for this standard are the implementors of the UVM base class library, the implementors of tools supporting the UVM base class library, and the users of the UVM base class library. (The PDF of this standard is available at no cost compliments of the IEEE GET program https://ieeexplore.ieee.org/browse/standards/get-program/page/series?id=80)

Document information

  • Standard from IEEE
  • Published:
  • Document type: IS
  • Pages
  • Publisher IEEE
  • Distributor IEEE
  • ICS 35.060
  • Technical Committee IEEE Computer Society / Design Automation

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