Standard

ISO/IEC 18372:2004 ED1

Dec 2004 Published

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Language English

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Abstract

The electronic version of this International Standard can be downloaded from the ISO/IEC Information Technology Task Force (ITTF) web site. The RapidIO architecture was developed to address the need for a high-performance low pin count packet-switched system level interconnect to be used in a variety of applications as an open standard. The architecture is targeted toward networking, telecom, and high performance embedded applications. It is intended primarily as an intra-system interface, allowing chip-to-chip and board-to-board communications at Gigabyte per second performance levels. It provides a rich variety of features including high data bandwidth, low-latency capability and support for high-performance I/O devices, as well as providing globally shared memory, message passing, and software managed programming models.

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Standard from IEC
Published: 15 December 2004
Edition: 1
Document type: IS
Pages
ISBN: 283187744X

Publisher IEC
Distributor IEC
ICS 35.200
ISO TC ISO/IEC JTC 1/SC 25

ISO/IEC 18372:2004 ED1

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