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Standard

IEEE 1296-1987

Withdrawn
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Abstract

New IEEE Standard - Inactive-Withdrawn. This standard describes a high-performance backplane bus intended for use in multiple processor systems. The bus incorporates synchronous, 32-bit multiplexed addreddata, with error detection and uses a 10 MHz bus clock. This design is intended to provide reliable state-of-the-art operation and to allow the implementation of cost-effective high performance VLSI for the bus interface. The standard defines memory, I/O, message, and geographic address spaces. The memory space supports single and block transfers. The message space defines a high-level protocol for transferring blocks of data (messages) as multiple packets of data (small data bursts; e.g., 32 bytes in one microsecond) over the bus. This provides a highperformance (e.g., 32 megabytes/second) interprocessor communication transfers among many different processors on the bus. Error detection and retry is provided for messages. This message passing design also allows a VLSI implementation, such that virtually all modules on the bus will utilize the bus at its highest performance - 32 to 40 megabytes/second. The standard provides geographic addressing for ease of configurability, initialization, and diagnostics.

Document information

  • Standard from IEEE
  • Published:
  • Withdrawn:
  • Document type: IS
  • Pages
  • Publisher IEEE
  • Distributor IEEE
  • ICS 35.200
  • Technical Committee IEEE Computer Society / Microprocessor Standards Committee

Product Relations

  • Refers: [3] IEC Pub 603-2 (1980), Connectors for Frequencies Below 3 MHz for Use with Printed Boards - Part 2: Two-Part Connectors for Printed Boards, for Basic Grid of 2.54 mm (0.1 in), with Common Mounting Features.
  • Refers: [2] IEC Pub 297-3 (1984), Part 3: Subracks and Associated Plug-In Units.
  • Refers: IEC Pub 297-1 (1986), Dimensions of Mechanical Structures of the 482.6 mm (19 in) Series-Part 1: Panel and Racks.