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Standard

IEEE 10861-1994

Withdrawn
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Abstract

New IEEE Standard - Inactive-Withdrawn. The operation, functions, and attributes of a parallel system bus (PSB), called MULTIBUS II, are defined. A high-performance backplane bus intended for use in multiple processor systems, the PSB incorporates synchronous, 32-bit multiplexed address/data, with error detection, and uses a 10 MHz bus clock. This design is intended to provide reliable state-of-the-art operation and to allow the implementation of cost-effective, high-performance VLSI for the bus interface. Memory, I/O, message, and geographic address spaces are defined. Error detection and retry are provided for messages. The message-passing design allows a VLSI implementation, so that virtually all modules on the bus will utilize the bus at its highest performance—32 to 40 Mbyte/s. An overview of PSB, signal descriptions, the PSB protocol, electrical characteristics, and mechanical specifications are covered.

Document information

  • Standard from IEEE/ISO/IEC
  • Published:
  • Document type: IS
  • Pages
  • Publisher IEEE/ISO/IEC
  • Distributor IEEE/ISO/IEC
  • ICS 35.160
  • Technical Committee IEEE Computer Society / Microprocessor Standards Committee

Product Relations

  • Refers: IEEE 1101-1987
  • Refers: IEC 603-2 : 1988, Connectors for frequences below 3 MHz for use with printed boards—Part 2.: Two-part connectors for printed boards, for basic grid of 2,54 mm (0,1 in), with common mounting features.
  • Refers: IEC 297-1 : 1986, Dimensions of mechanical structures of the 482,6 mm (19 in) series—Part 1.: Panels and racks.
  • Refers: -DIN publications are available from the Deutsches Institut für Normung, Burggrafenstrasse 6, D-1000 Berlin 30, Germany
  • Refers: IEC 297-3 : 1984, Dimensions of mechanical structures of the 482,6 mm (19 in) series—Part 3.: Subracks and associated plug-in units.
  • Refers: DIN 41612, Two Part Connectors for Printed Board, GRIB, to 54 mm, Common Mounting Features, Survey of Types.