Standard

HD 576 S1

Sep 2015 Published

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Language English

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Abstract

The VSB bus was designed to meet the needs of multiprocessor systems based on high-performance 32-bit microprocessors built up from board assemblies. lt includes a high-speed asynchronous data transfer bus allowing masters to direct the transfer of binary data to and from slaves according to 4 kinds of cycles: address-only, single-transfer, block-transfer and interrupt-acknowledge cycles. It also includes an arbitration bus enabling arbiter modules and/or requester modules to coordinate the use of the data-transfer bus according to two arbitration methods (series or parallel).

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Standard from SFS-sähkö
Published: 14 September 2015
Edition: 1
Document type: IS
Pages
ISBN:

Publisher SFS
Distributor SFS-sähkö
Technical Committee CLC/SS V24

HD 576 S1

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